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Texas Instruments Layout Engineer 2026: Bengaluru Semiconductor Role

Texas Instruments Bengaluru is hiring a Layout Engineer for semiconductor IC layout, floorplanning, ESD and PAD-ring design work.

Shila Choudhary
Written by
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Editorial teamRegal Editorial Team
Dilip Kumar
Final review byDilip Kumar
Application deadline
Deadline not announced
Last date: Not announced
VacanciesSee notification
QualificationBachelor’s Degree;…
LocationBengaluru, Karnataka, India

Recruitment Snapshot

Applications open

Texas Instruments Bengaluru is hiring a Layout Engineer for semiconductor IC layout, floorplanning, ESD and PAD-ring design work.

EmploymentFull Time
LocationBengaluru, Karnataka, India
Organisation: Texas Instruments Advertisement No.: Job ID 25018741 Official Notification Date: 28 Oct 2026

Recruitment timeline

Application window
1Official notification published28 Oct 2026
2Applications opened28 Oct 2026
Published on Regal Naukri

Texas Instruments has opened a fresh Layout Engineer opportunity in Bengaluru, Karnataka under Job ID 25018741, posted on 28 October 2026. The role is directly connected to semiconductor physical design and IC layout, making it highly relevant for engineers who want to enter or grow within VLSI implementation rather than generic software development. According to the official TI job page, the engineer will develop multi-dimensional layouts and detailed semiconductor-device drawings from design schematics, work with CAD-based layout tools, check dimensions and specifications, and verify completed layout artwork or digitized plots. TI also highlights practical skills in floorplanning, block-layout closure, ESD knowledge, PAD-ring completion, IO placement and performance/area/quality optimization. The official page lists Bachelor’s Degree as the degree level. It does not publish a vacancy count, salary figure, experience range or application deadline, so none of those details are invented here. This role is best suited to candidates with academic or project exposure to VLSI physical design, IC layout, analog/digital layout, floorplanning, DRC/LVS, ESD, PAD-ring planning and semiconductor CAD tools. Applicants should use the official TI careers portal and tailor their resume around hands-on layout or physical-design work.

Job Overview

ParticularDetails
CompanyTexas Instruments
RoleLayout Engineer
Job ID25018741
Date Posted28 October 2026
LocationBengaluru, Karnataka
Job CategoryEngineering – Product Development
Degree LevelBachelor’s Degree
Vacancy CountNot specified
SalaryNot disclosed
Experience RequirementNot stated
Application DeadlineNot stated

Key Work Areas

  • Semiconductor-device layout from schematics
  • CAD-based physical design
  • Floorplanning and block-layout closure
  • ESD-aware layout
  • PAD-ring completion and IO placement
  • Performance, area and quality optimization
  • Drawing/specification checks and layout verification

Basic Qualification

The official job page lists Bachelor’s Degree as the degree level.

Useful Skills

VLSI physical design, IC layout, floorplanning, DRC/LVS, ESD, PAD-ring design, IO placement and semiconductor CAD tools.

Salary

Not disclosed on the official page.

How to Apply

Apply through the official Texas Instruments job page.

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